EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 40

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
4.4.5
4.4.6
4.4.7
40
0954B–BDC–12/09
DMUX Power Reduction Mode (SLEEP)
DMUX Clock input Delay Cell (CLKDACTRL)
DMUX Built-In Test
The power reduction (SLEEP) mode allows the user to reduce the power consumption of the device
(DMUX part in Sleep mode). In this mode, the DMUX part consumption is reduced by 0.9W.
The Power reduction mode is active when SLEEP is low.
The device is in normal mode when SLEEP is high.
When the device is not used, minimal Power consumption is obtained with NAP (ADC part) and SLEEP
(DMUX part) modes used simultaneously.
A tunable delay cell (CLKDACTRL) is in serial on the 11 Bit DMUX Data path to fine tune the data vs.
clock alignment at the interface between the ADC and the DMUX.
The delay is controlled via the CLKDACTRL pin. This delay can be tuned around default center value. It
ranges from –100 ps to 100 ps for CLKDACTRL varying from V
This function results in a delayed internal clock signal.
This pin must always be biased and it is recommended to set CLKDACTRL at V
With the recommended value, it is normally not necessary to tune the CLKDACTRL voltage over the full
specified clock rate, temperature range and power supply voltage range.
Figure 4-12. DMUX Clock Input Cell Block Diagram
The Built-In Self Test allows to test rapidly the DMUX block of the device.
It is activating via the BIST bit (active low) a checker board like pattern generator.
When this signal is left floating, the BIST is inactive.
When in BIST mode, a clock must be applied to the device, which can be set to 1:2 or 1:4 mode. The
output clock mode DRTYPE can be either DR or DR/2.
In the BIST mode, all the bits are either all at low or high level (even and odd bits are in phase opposi-
tion) and transition every new cycle.
In order to have a deterministic output sequence, it is necessary to perform an asynchronous reset.
CLK/CLKN
CLKDACTRL
2
(-100 to 100 ps)
Delay
CCD
/ 3 to 2 × V
2
CCD
Internal
clock signal
e2v semiconductors SAS 2009
CCD
/ 3.
/3.