EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 55

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

5.3.1
e2v semiconductors SAS 2009
Driving the EV10AS150A with a Sinewave Clock Input
The SNR rolloff in the high input frequency region (2
The ADC sampling jitter is 120 fs rms, to be RSS summed with external sampling clock jitter:
To achieve optimum SNR in the 2
ewave requirements are mainly two-fold:
The external sinewave clock signal phase noise and clock signal slew-rate.
The Single Side Band (SSB) phase noise floor of the reference sinewave clock signal shall not exceed
155 dBc/Hz (at 1 MHz from carrier).
The slew-rate of the 2.5 GHz clock input shall not be lower than 5 GV/s at 2.5 GHz frequency.
Accordingly, at 2.5 GHz sampling clock frequency, a sinewave clock input can be directly entered pro-
vided the sinewave amplitude is 0.632 Vpp minimum into the 100Ω differential output to ensure 5 GV/s
minimum slew-rate, and 155 dBc/Hz phase noise floor.
Sinewave Clock slew-rate effect on SNR:
Due to very fast internal slew-rates of regeneration stages, a sinewave clock can be entered without
impacting the SNR so far the sinewave slew-rate is higher than 5 GV/s minimum (8 GV/s
recommended).
These fast slewing front-end clock buffer regeneration stages provides lowest internal rms time domain
jitter, as illustrated by the following relationship:
Rms(time jitter) = Rms(voltage noise) / Rms(slew-rate)
Assuming the ADC clock input is driven by a transformer (single-ended unbalanced 50Ω to balanced
100Ω differential), the minimum clock input power shall not be lower than –3 dBm into 50Ω input imped-
ance = 0.45 Vpp at transformer input yielding 0.45 Vpp.SQRT(2) = 0.632 Vpp across 100Ω differential
outputs applied to the ADC.
A minimum swing of 0.632 Vpp at 2.5 GHz corresponds to a minimum slew-rate of nearly 5 GV/s at
2.5 GHz.
Therefore, the 2.5 GHz external sinewave clock signal voltage amplitude applied across the 100Ω termi-
nation shall not be lower than 0.632 Vpeak to peak for optimum SNR performance in the 1
Nyquist.
For sinewave clock frequencies lower than 2.5 GHz, the sinewave amplitude shall be increased accord-
ingly, to preserve the minimum slew-rate of 5 GV/s, without exceeding 2 Vpp maximum operating
amplitude applied to the differential clock input. For example, with a 1.25 GHz sinewave clock, to keep
the same slew-rate of 5 GV/s, the minimum voltage amplitude to be applied to the ADC clock input shall
not be lower than 2 × 0.632 Vpp = 1.264 Vpp across the 100Ω differential clock inputs, corresponding to
+ 3 dBm into 50Ω transformer input (which is twice the clock input power of a 2.5 GHz sinewave input).
Typical recommended clock input power for a 2.5 GHz sinewave clock for optimum SNR over full tem-
perature range shall be +1 dBm into 50Ω transformer input impedance, which corresponds to 0.710
Vpp.SQRT(2) = 1 Vpp across 100Ω across differential outputs applied to the ADC clock inputs. This cor-
responds to a slew-rate of 7.85 GV/s at 2.5 GHz.
Therefore, typical recommended slew-rates to ensure flat SNR over operating temperature range shall
be in the range of 8 GV/s.
nd
Nyquist (e.g; SNR > 48 dB at Fin = 3000 MHz, the external clock sin-
nd
and 3
rd
Nyquist) is dictated by sampling jitter:
EV10AS150A
0954B–BDC–12/09
st
and 2
55
nd