EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 57

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

e2v semiconductors SAS 2009
–130 dB + 10.log(10
Integrated double SSB phase noise power in radians (rms):
SQRT(2.10
To be compared with 1,86.10
total RSS summed phase noise from 10KHz to 5.5 GHz is:
SQRT ((1,86.10
Therefore the close-in phase contribution remains negligible. The close-in phase noise (1/f2 and 1/f3)
contributions can also be neglected since this type of phase noise is related only to long term jitter drift
effects which are not of concern here regarding the registration length of the Digital Data.
For example, considering the registration length time window for a 32K FFT at 2.5 Gsps:
32768x400 ps = 13.107 µs, corresponding to 76.3 KHz.
As a result, the close-in phase noise below 70 KHz has not to be taken into account for the integration.
As a conclusion, considering a phase noise floor between 1 MHz and 5.5 GHz, any clock source phase
noise floor better than 155 dBc/Hz will improve somewhat the SNR:
For example, a 160 dBc/Hz phase noise clock source will feature only 67 fs rms time domain jitter for a
2.5 GHz carrier, and a 165 dBc/Hz clock source will feature only 38 fs rms.
In these cases, the external clock source contribution to total jitter will be negligible, compared to the 120
fs rms intrinsic jitter of the ADC, and SNR performance in the 2
Better SNR performance over frequency will then necessarily go through the improvement of intrinsic
ADC jitter (< 50 fs rms for instance).
On the other hand, using a lower performance phase noise floor sinewave source will cause extra rolloff
of the SNR in 2
Example: 150 dBc/Hz phase noise will feature a time domain jitter of 188 fs rms time domain jitter for a
2.5 GHz carrier, and a 145 dBc/Hz phase noise will feature 375 fs rms time domain jitter at 2.5 GHz.
Therefore the impact on SNR (and therefore ENOB performance) for very high analog input frequencies
is no more negligible against ADC intrinsic jitter, and the SNR performance will be impacted in these
cases.
As a conclusion, the recommended phase noise floor shall be at least 155 dBc / Hz for optimum SNR
performance over multiple Nyquist zones. Any improvement in phase noise floor will help to save a few
dBs especially in the 2
Note:
If a fixed clock source can be used, (i.e.: non swept clock), the sinewave clock source can be band-pass fil-
tered to further improve the phase noise floor.
–70 / 10
nd
–03
) = 0,447.10
Nyquist region.
radians)2 + (0,447.10
6
–10
nd
and 3
4
) = –130 + 60 dB = –70 dB
–03
–03
rd
radians (rms)
Nyquist zones.
radians (rms) 155 dBc/Hz phase noise integrated over 5.5 GHz. The
–03
radians)
2
) = 1,91.10
nd
–03
and 3
radians
rd
Nyquist will be improved.
EV10AS150A
0954B–BDC–12/09
57