EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 2

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
Applications
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1. Block Diagram
The EV10AS150A combines a 10-bit 2.5 Gsps fully bipolar analog-to-digital converter chip, driving a fully bipolar DMUX
chip with selectable Demultiplexing ratio (1:2) or (1:4). The 5 GHz full power input bandwidth of the ADC allows the direct
digitization of up to 1 GHz broadband signals in the high IF region, in either L_Band or S_Band. The EV10AS150A features
7.8 effective bit and close to –58 dBFS spurious level at 2.5 Gsps over the full 1
Scale (–1 dBFS), and 8.1 bit ENOB at –6 dBFS in the 2
The 1:4 demultiplexed digital outputs are LVDS logic compatible, which allows easy interface with standard FPGAs or
DSPs. The EV10AS150A operates at up to 2.5 Gsps in DMUX 1:4 and up to 2.0 Gsps in 1:2 DMUX ratio (The speed limita-
tion with 1:2 DMUX ratio is mainly dictated by external data flow exchange capability at 2 × 1 Gsps with available FPGAs).
The EV10AS150A ADC+DMUX combo device is packaged in a 25 × 35 mm Enhanced Ball Grid Array EBGA317. This
Package is based on multiple layers which allows the design of low impedance continuous ground and power supplies
planes, and the design of 50Ω controlled impedance lines (100Ω differential impedance). This package has the same Ther-
mal Coefficient of Expansion (TCE) as FR4 application boards, thus featuring excellent long term reliability when submitted
to repeated thermal cycles.
2
Direct Broadband RF Down Conversion
Wide Band Communications Receiver
High Speed Instrumentation
High Speed Data Acquisition Systems
0954B–BDC–12/09
Figure 1-1.
3 WSI
DRR (ADC Reset)
3 WSI RESET
DRTYPE (Dual Data Rate)
BIST (Pattern Generator)
SDATA
SLDN
SCLK
VINN
CLKN
Functional Block Diagram
VIN
STAGG (Latency)
CLK
SLEEP (DMUX)
RS (Ratio Sel)
Sampling
delay
Offset
Gain
100
3-wire Serial
Interface
(3WSI)
DAC
DAC
DAC
8-bit
8-bit
8-bit
nd
T/H
Nyquist zone.
Tunable
Delay
line
100
Circuitry
Timing
& SDA
Tunable
Delay line
CLKDACTRL
st
Demultiplexer
Nyquist for large signals close to ADC Full
1:2 or 1:4
ASYNCRST
(Dmux Reset)
e2v semiconductors SAS 2009
20
2
20
2
20
2
20
2
2
Port A
AOR/AORN
DRA/DRAN
Port B
BOR/BORN
DRB/DRBN
Port C
COR/CORN
DRC/DRCN
Port D
DOR/DORN
DRD/DRDN
DR/DRN