EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 45

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

4.5.6
4.5.7
4.5.8
e2v semiconductors SAS 2009
Sampling Delay Adjust Function (SDA) – ADC Interleaving
ADC Gain Control
Offset Control
This function is of most importance for applications based on time interleaving of multiple ADCs, in order
to increase the actual sampling rate. In interleaved system the channels relative phasing has to be
matched finely to avoid intermodulation spurs. The SDA function is monitored through the 3 Wire Serial
Interface (3WSI), for remote fine alignment of ADC Aperture delays.
The SDA fine tuning has to be done after proper alignment of ADC Gains and Offsets, also monitored by
the 3WSI.
A control voltage is applied on the tunable delay line, through embedded control DACs: 2 Bit DAC
(coarse tuning) and 8 Bit DAC (fine tuning). The coarse 2 Bit DAC allows for coarse alignment of the
ADCs aperture delays, with a step (resolution) of 30 ps. The 8 Bit control DACs allows for fine phase
alignment of ADCs, with a resolution of 30 ps/256 = 117 fs. This is more than enough for very fine phase
alignment of multiple ADCs. Once tuned, the ADCs track each other versus temperature.
It is reminded that the ADC intrinsic jitter is 120 fs rms, (with SDA = OFF).
The sampling delay adjust enables a tuning of the aperture delay of each channel over a range of 120 ps
with a first coarse tuning over a range of 90 ps and then a fine tuning on 8 bit over a range of 30 ps for
better accuracy of the settings.
It is pointed out that the ADC intrinsic jitter is 120 fs rms if SDA is turned OFF, and becomes 150 fs rms
if SDA is turned ON, and 170 fs rms if SDA is fully tuned. This is related to extra delay cells in the sam-
pling clock path, which are bypassed if SDA is OFF. If the SDA is turned on, an amount of + 60 ps extra
time delay adds onto the sampling clock path.
For reference, the measured SNR at Fin = 2500 MHz (–1 dBFS) is 50 dB with SDA = OFF, 49.2 dB with
SDA turned on, and 48.5 dB with SDA turned ON and fully tuned.
For optimum dynamic performance (low jitter), it is recommended to disable SDA (Mode SDA OFF).
Figure 4-14. Programming the SDA Tunable Delay Line Through the 3WSI
The 3-Wire bus interface also allows for adjusting the gain by enabling a fine tuning by ±0.5 dB and an
8-bit resolution.
The 3WSI allows to control the offset of the ADC with a tuning range of ± 20mV, and an 8 bit resolution.
= 120 fs rms
SDA = OFF
(ADC Jitter
60 ps
SDA = ON
(ADC Jitter
= 150 fs rms
00
30 ps
SDA Coarse tuning
on 2 Bit: 30 ps step
01
30 ps
SDA = ON
10
30 ps
SDA = ON
fully tuned
(coarse)
SDA Fine tuning
on 8 Bit : 117 fs resolution
11
30 ps
EV10AS150A
SDA = ON
fully tuned
(coarse + fine)
ADC Jitter =170 fs
0954B–BDC–12/09
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