EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 56

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
Maximum operating clock input power shall not exceed + 7 dBm, which corresponds to 2 Vpp on differ-
ential 100Ω clock input. This corresponds to slew-rates of 15.7 GV/s
Maximum ratings for differential clock input is 3 Vpp which corresponds nearly to +11 dBm maximum
clock input power.
Sinewave Clock Phase noise vs. time domain jitter effect on SNR rolloff at high input frequencies:
The SNR due to ADC intrinsic clock jitter contribution only (i.e. 120 fs rms), excluding external clock
source jitter (jitter free external clock source), is 50 dB at Fin = 2500 MHz, –1 dBFS.
Taking into account the external clock source time domain jitter contribution on SNR performance, the
ADC intrinsic clock jitter of 120 fs rms has to be RSS summed to the external rms clock jitter, yielding to
total sampling clock Jitter:
For example with a 100 fs rms external clock source jitter, the total sampling clock jitter will be
2
2
SQRT(120
+ 100
) = 156 fs rms.
With a 120 fs rms clock source jitter, the total jitter will be 170 fs rms:
For the EV10AS150A, the measured SNR at Fin = 2500 MHz for –1 dBFS analog input amplitude is
50 dB with a jitter free external clock source, (taking only into account the ADC intrinsic jitter of 120 fs
rms). With 120 fs rms external clock source time domain jitter RSS summed with the 120 fs rms intrinsic
ADC clock jitter, (leading to 170 fs rms total jitter), the measured SNR becomes 48.5 dB.
Relationship between sinewave clock source phase noise and time domain jitter:
The 100 fs rms external time domain jitter corresponds approximately to an external sinewave clock
source with (white) phase noise floor spectral density of 155 dBc / Hz, integrated from 1 MHz up to
5.5 GHz:
The 5.5 GHz upper limit of integration corresponds to the ADC clock input bandwidth. The 1 MHz lower
limit of integration corresponds to the flat section of white phase noise, excluding 1/f and close in phase
st
noise contribution for 1
order calculations.
The integration bandwidth for the phase noise floor is taken from 1 MHz up to 5.5 GHz ADC clock input
bandwidth, leading to:
Integrated SSB phase noise floor spectral density: 155 dBc/Hz, 1 MHz to 5.5 GHz:
9
6
–155 dB + 10.log(5.5.10
–1.10
) = –155 + 97.4 dB = –57.6 dB.
2
This corresponds to the Single Side Band (SSB) phase noise power spectral density 10.log(Rad
/Hz)
expressed in dBc/Hz, integrated over nearly 5.5 GHz. The total integrated Double Side Band phase
noise power expressed in radian (rms) is:
–57.6 / 10
–03
SQRT (2.10
) = 1,86.10
radians (rms).
In time domain, the rms jitter is obtained by dividing the total phase noise power (radians rms) by the car-
rier frequency.
–03
For example, with a 2.5 GHz sinewave clock carrier, the time domain jitter will be 1,86.10
radians
(rms) / 2.π.2,5 GHz = ~ 118 fs rms
Therefore for a given constant phase noise floor, the external clock source time domain jitter will be
slightly better when increasing clock frequency (due to faster signal slew-rate).
The 1/f phase noise contribution from 10 KHz to 1 MHz can be neglected so far the mean noise level in
this region is below 130 dBc / Hz:
Integrated SSB mean phase noise spectral density: 130 dBc/Hz, 10 KHz to 1 MHz:
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e2v semiconductors SAS 2009