EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 13

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EVX10AS150ATP

Manufacturer Part Number
EVX10AS150ATP
Description
Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
Manufacturer
ETC-unknow
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EVX10AS150ATP
Manufacturer:
E2V
Quantity:
20 000
2.5
Table 2-10.
e2v semiconductors SAS 2009
Parameter
Switching Performance and Characteristics
Maximum Clock Frequency
DRTYPE = DR/2, 1:2 mode
DRTYPE = DR,
DRTYPE = DR/2 1:4 mode
DRTYPE = DR
Minimum clock frequency
Transient and Switching Characteristics
Switching characteristics
1:2 mode
1:4 mode
Table 2-8.
Table 2-9.
Note:
Parameter
Spurious Free Dynamic Range
Fs = 2.5 Gsps Fin = 500 MHz
Fs = 2.5 Gsps Fin = 1245 MHz
Fs = 2.5 Gsps Fin = 2495 MHz
Two-Tone 3
IMD3 (
at
Fin1 = 790 MHz, Fin2 = 800 MHz
Fin1 = 1550 MHz, Fin2 = 1560 MHz
Fin1 = 2500 MHz, Fin2 = 2510 MHz
Signal independent spurious level
(Fclk/4 with 1:4 DMUX Ratio)
(
Single-ended driven analog input (50Ω)
(ADC full scale input power:
Ain =
-> Refer to
Ain = –13 dBFS, +1 dBm differential clock (1 Vpp in 100Ω at 2.5 GHz), 50% external duty cycle, Binary output mode
-> Refer to
Parameter
TRANSIENT PERFORMANCE
Bit Error Rate
ADC settling time (± 2%)
Overvoltage recovery time
ADC step response
Rise/Fall Time (10–90%)
1 dBFS Analog Input)
7 dBFS each tone, Fs = 2.5Gsps
): (2f1-f2, 2f2-f1)
3 dBFS, +1 dBm differential clock (1 Vpp in 100Ω at 2.5 GHz), 50% external duty cycle, Binary output mode
1. Measured with SDA OFF
rd
Table 2-7 on page 10
Table 2-7
ADC Bit Error Rate is related to internal regeneration latches indecision (for analog inputs very close to
latches threshold), which may produce large amplitude output errors.
The probability of error is measured at 2.5 Gsps maximum operating frequency.
order Intermodulation distortion
(1)
Dynamic Converter Characteristics with Single Ended Analog Input (Continued)
Transient Characteristics
(same performance with single ended or differential analog input with –13 dBFS input level)
2 dBm)
(same performance with single ended or differential analog input with –3 dBFS input level)
Test Level
Test Level
4
4
4
4
4
4
1
1
4
Level
Test
4
4
4
4
4
Symbol
Symbol
Fs MAX
Fs MIN
BER
ORT
TS
Symbol
IMD3(
|SFDR|
Fclk/4
)
Min
Min
2.0
2.0
2.5
2.5
50.0
51.0
50.0
52.0
52.0
54.0
Min
10
Typ
80
–12
Typ
55.0
57.0
54.0
58.0
58.0
60.0
Typ
72
74
EV10AS150A
Max
0954B–BDC–12/09
350
400
100
Max
500
Max
–69
–71
Error/sample
Unit
ps
ps
ps
dBFS
dBFS
Gsps
Msps
dBm
Unit
Unit
dBc
13

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