EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 16

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
2.6.5
2.6.6
16
0954B–BDC–12/09
Alignment Between Data Ready and Data Including Skew Management
Minimum Available Time Width Between Data and Data Ready (TD1, TD2)
In staggered mode, the differential delays are (TOD1-TDR1), (TOD2-TDR2), (TOD3-TDR3), (TOD4-
TDR4). See
Therefore the absolute delay values TOD and TDR are not actually of interest: only the time difference
TOD-TDR has to be actually considered.
The measurement of the relative time difference is easy with matches probes, whereas absolute timings
are very difficult to measure.
If the propagation time delays (trace lengths for digital data outputs and Data Ready outputs are well
matched, together with ideal TOD = TDR, we shall measure ideally TOD-TDR = 0 at application board
outputs (FPGA or DSP incoming signals).
Real TOD-TDR excluding skew between different data is ± 50 ps typical, and ± 100 ps max.
In simultaneous mode, one common Data Ready pulse (DR, DRN) is output for all 4 differential Output
Ports A,B,C,D. Therefore the skews of the 4 differential data ports have to be as low as possible:
the skews of the 4 differential output ports due to ADC Package and internal ADC Buffers is less than ±
25 ps max (measured at Package output Balls).
The external skews due to track length differences of the external 100Ω controlled impedance lines),
shall be kept as low as possible.
For example, (considering 3.3 ps/mm propagation time in vacuum), the signal propagation time in
a different medium of dielectric constant ε
6.6 ps/mm: a 3 mm skew in length between the 40 differential data will result in a 3 mm × 6.6 ps/mm =
~ 20 ps skew, to be added to the ±25 ps skew due to the ADC (Package outputs).
The total skew (ADC + board) will be in this case 50 ps + 20 ps = 70 ps = ± 35 ps in actual skew at FPGA
incomings.
Since TOD-TDR is ± 50 ps typical, and ± 100 ps max, TOD-TDR shall be added to the total data skew,
(ADC and board), leading to:
(TOD-TDR) + Tskew(total) = (± 100 ps) + (± 35 ps) = (± 135 ps) maximum uncertainty on positioning of
differential Data Ready signal rising edge (DR, DRN), pulse within Data pulse.
In staggered mode, the 4 (four) out-of-range bit function for the 4 (four) Ports A,B,C,D are respectively
re-allocated to the Data Ready function, available for each output Port, since latency is different, namely:
Port A (AOR, AORN); Port B (BOR, BORN); Port C (COR, CORN); Port D (DOR, DORN)
is respectively replaced by: (DRA, DRAN), (DRB, DRBN), (DRC, DRCN), (DRD, DRDN).
The output propagation delays of the 4 Data Ready pulses (TDR1, TDR2, TDR3, TDR4) are identical to
the TDR output propagation delay in simultaneous mode, and are matching the Digital Data propagation
delays of the 4 Output Ports over temperature.
The relative differential timing values (TOD1-TDR1), (TOD2-TDR2), (TOD3-TDR3), (TOD4-TDR4) are
identical to the TOD - TDR differential timing of the simultaneous mode. Skew for port A, B, C, D are con-
sidered for 10 bit data in staggered instead of 44 bit of data in simultaneous. Skew between 10 data is
slightly better in staggered mode. To simplify calculation skew values of previous section shall be
applied.
At 2.5 GHz sampling rate, the time difference between zero crossing point of change of differential data
and differential Data Ready output clock rising edge (centered within data pulse) is defined by TD1. The
time difference between differential data clock rising edge and next point of change of the differential
data output is defined by TD2.
Figure 2-4 on page
19.
r
= 4 (at 10 GHz), is yielding to SQRT(ε
e2v semiconductors SAS 2009
r
) × 3.3 ps/mm =