EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 36

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
4.4.1
4.4.2
36
0954B–BDC–12/09
DMUX Ratio
DMUX Data Ready Output Clock Selection (DRTYPE)
The demultiplexer ratio is programmable thanks to the RS Ratio selection signal.
Table 4-3.
Figure 4-4.
Figure 4-5.
DMUX Data Ready Output Clock is used to latch EV10AS150A output data.
Two modes for the output Data clock rate can be selected (via DRTYPE):
This is illustrated in the following figures:
Figure 4-6.
• DR mode: The output data clock frequency is 1/4
• DR/2 mode: The output data clock frequency is 1/8
Ratio), and switches at twice the output data rate. Therefore only the rising edge is considered as
active for output data registering (Rising edge of differential output Data clock (DR, DRN) is located at
center of the digital data pulse).
Ratio), the output clock switches at same rate as the digital data. Therefore, both output Data clock
rising and falling edges are active for output data registering (Rising and Falling edge of differential
output Data clock (DR, DRN) are located at center of the digital data pulse).
Data Out
DMUX Ratio Selection Settings
DMUX in 1:2 Ratio
DMUX in 1:4 Ratio
DR Mode
DR
Input Words:
1, 2, 3, 4, 5, 6, 7, 8…
Input Words:
1, 2, 3, 4, 5, 6, 7, 8, 9…
RS
0
1
1:2
1:4
th
th
the ADC Clock frequency (assuming 1:4 DMUX
the ADC Clock frequency (assuming 1:4 DMUX
Output Words:
Port A
Port B
Port C
Port D
Output Words:
Port A
Port B
Port C
Port D
1
2
Not Used
Not Used
1
2
3
4
3
4
5
6
7
8
DMUX Ratio
5
6
9
10 …
11 …
12 …
1:2
1:4
7
8
…
e2v semiconductors SAS 2009
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