EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 35

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

4.4
e2v semiconductors SAS 2009
Control Signal Settings (DMUX)
The SLEEP, RS, STAGG, BIST and DRTYPE control signals use the same input buffer.
SLEEP, STAGG, BIST are activated on Logic Low (10Ω Grounded), and deactivated on Logic High (10
KΩ to Ground, or tied to V
This is illustrated in Figure hereafter:
Figure 4-3.
Table 4-2.
Note:
Function
BIST
SLEEP
STAGG
RS
DRTYPE
10
1. Refer to
GND
Low Level (‘0’)
Control Signal Settings (SLEEP, RS, STAGG, BIST and DRTYPE)
DMUX Mode Settings - Summary
Table 2-4 on page 7
Logic Level
Signal Pin
Control
0
1
0
1
0
1
0
1
0
1
CCD
= 3.3V, or left floating).
10 KΩ to ground
10 KΩ to ground
10 KΩ to ground
10 KΩ to ground
10 KΩ to ground
10Ω to ground
10Ω to ground
10Ω to ground
10Ω to ground
10Ω to ground
for logical levels.
Static drive
N/C
N/C
N/C
N/C
10 K
Electrical Level
GND
Dynamic drive
V(DRTYPE) = V
V(DRTYPE) ≥ V
V(STAGG) = V
V(STAGG) ≥ V
V(SLEEP) = V
V(SLEEP) ≥ V
V(BIST) ≥ V
V(BIST) = V
V(RS) ≥ V
V(RS) = V
Signal Pin
Control
IH
IL
IH
IL
High Level (‘1’)
IH
IH
IL
(1)
IL
IH
IL
Connected
Not
Description
BIST: Checker board on output
data
Normal conversion
Power reduction mode (the
outputs are fixed at an
arbitrary LVDS level)
Normal conversion
Staggered mode
Simultaneous mode
1:2 ratio
1:4 ratio
DR/2 mode
DR mode
EV10AS150A
0954B–BDC–12/09
Signal Pin
Control
35