EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 18

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
Figure 2-3.
18
DMUX
ADC
Digital Outputs
Port A, Port B, Port C, Port D
VIN
ADC CLK
(DR, DRN) Data Ready
(in DR mode )
0954B–BDC–12/09
(B0, B0N)...(B9, B9N)
(D0, D0N)...(D9, D9N)
(A0, A0N)...(A9, A9N)
(C0, C0N)...(C9, C9N)
Timing Diagram Simultaneous mode, 1:4 DMUX Ratio
DMUX Even Latches
ADC Data Clock
( internal Fclock/2)
Clock/4 synchronised
on falling edges of Clock
Clock/8 synchronized
with output Data
on falling edges of Clock
DMUX Odd Latches
Digital Outputs
( internal )
Clock/8 shifted
+ 2 clock cycles
Port Select A
Port Select B
Port Select C
Port Select D
Digital outputs : Port A
Digital outputs : Port B
Digital outputs : Port C
Digital outputs : Port D
N
2 Tclock
N-4
7.5 clock cycles (ADC+DMUX)
4 clock cycles: ADC Pipeline Delay
TA = +350 ps
ADC : 4 cycles
N-3
N - 1
N-2
N - 2
-2
N-1
3.5 clock cycles
-1
N -8
N -7
N -6
N -5
N - 3
N
DMUX : 3.5 cycles
N - 4
N - 3
N - 2
N - 1
ADC Pipeline Delay: 4 clock cycles
ADC+1:4 DMUX Pipeline Delay: 7.5 clock cycles on Port A
N
N - 4
N+1
1
N
N+2
2
N + 1
N+3
2 Tclock
3
N + 2
1:4 DMUX Pipeline Delay on Port A
N -4
N -3
N -2
N -1
TOD
N+4
4
N + 1
N + 3
N + 2
N + 3
N+5
N
N + 4
Tskew
5
N+6
TDR
6
N + 5
Port A : N,
Port B : N+1
Port C : N+2
Port D :
TD1 TD2
N + 6
7
N + 6
N + 7
N + 7
N + 5
N+4
N+3
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Tskew