EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 33

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

4.3
e2v semiconductors SAS 2009
RESETs and ADC Synchronization
There are three reset signals available on the device to start the device properly:
DRR, RESET and ASYNCRST are mandatory for proper device initialization.
Please refer to the paragraph 5.5 for more information on how to implement these reset functions.
DRR is active high or low depending on bit D8 of state register at address 0110 while ASYNCRST is
active high.
It is mandatory to apply ASYNCRST while DRR is active.
2 sequences are recommended depending on the applications.
During this sequence 1, the clock can be running or not running. But pipeline delay up to ADC outputs
will not be deterministic.
With this sequence 2, all ADCs will start on the first rising edge of the clock and they will be
synchronized.
• DRR (Data Ready Reset) is used to reset and synchronize the Data Ready Output Clock of the ADC.
• ASYNCRST is an asynchronous reset used to synchronize the DMUX so that the data are outputted
• RESET is a signal used to reset (load default settings) the 3 Wire Serial Interface (3WSI), see
• Sequence 1: to be used in the case where multiples ADCs synchronization is not needed
1. Perform a RESET on ADC (DRR active low or high depending on 3WSI settings). Maintain DRR
2. While DRR is active, perform an asynchronous reset of the DEMUX (ASYNCRST high).
3. Release ASYNCRST (ASYNCRST low) (minimum pulse width is 3ns)
4. Release DRR (minimum DRR pulse width is 3.5ns)
5. 3WSI interface can then be programmed if needed.
• Sequence 2: to be used in the case where multiples ADCs synchronization is needed
1. Apply a running clock in order to initialize ADC clock path
2. Stop ADC clock at low level
3. Perform a RESET on ADC (DRR active low or high depending on 3WSI settings).
4. Maintain DRR active up to step 7.
5. While DRR is active, perform an asynchronous reset of the DEMUX (ASYNCRST high).
6. Release ASYNCRST (ASYNCRST low) (minimum pulse width is 3ns)
7. Release DRR (minimum DRR pulse width is 3.5ns)
8. Restart ADC clock
9. 3WSI interface can then be programmed if needed.
DRR ensures that the first edge of the ADC output Data clock after DRR reset pulse is always a rising
edge. This ensures that the first Data for N sampled after ADC reset corresponds to the first
acquisition in the DMUX.
on the right order (Port A, then Port B, then Port C and then Port D). It is also necessary to have a
deterministic sequence in BIST mode.
4.5.2.
active up to step 4.
EV10AS150A
0954B–BDC–12/09
Section
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