EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 39

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

4.4.4
e2v semiconductors SAS 2009
Out-of-range Bit and Data Ready Output Clocks
Figure 4-11. Staggered Mode in 1:4 Ratio (STAGG = 0)
In simultaneous output mode:
The (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) and
(DOR/DRDN, DORN/DRD) signals are used to add the out-of-range bit to the ADC output data.
On each port (A, B, C, D) the out-of-range bit (*OR/*ORN) indicates (logic “1”) when the analog input
overrides the ADC 0.5 Vpp Full Scale voltage span, in case of underflow or overflow.
When the analog input exceeds the positive full scale, the 10 bit digital outputs data remain at high logi-
cal state, with (*OR,*ORN) at logical one. When the analog input falls below the negative full scale, the
10 bit digital outputs data remain at logical low state, with (*OR,*ORN) at logical one again.
In Staggered output mode:
The (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) and
(DOR/DRDN, DORN/DRD) signals will output the Data Ready Output Clock signal (one for each port),
centered on the corresponding Data.
In this case, the overflow can be computed with all 10 digital output data detection at logic “1”, (Binary
mode), and underflow can be computed with all 10 digital output data detection at logic “0” (Binary
mode).
In 1:2 DMUX Ratio, DR/DRN and DRB/DRBN are identical.
In 1:4 DMUX Ratio, DR/DRN and DRD/DRDN are identical.
Data Out Port C
Data Out Port D
Data Out Port A
Data Out Port B
in DR/2 mode
in DR/2 mode
in DR/2 mode
in DR/2 mode
in DR/2 mode
in DR mode
in DR mode
In DR mode
in DR mode
in DR mode
DRC
DRC
DRD
DRD
DRA
DRA
DRB
DRB
DR
DR
N - 2
N - 1
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
EV10AS150A
0954B–BDC–12/09
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