EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 21

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

2.9
e2v semiconductors SAS 2009
(Fs max)
(Fs min)
(BER)
(FPBW)
(SSBW)
(SINAD)
(SNR)
(THD)
(SFDR)
(ENOB)
(DNL)
(INL)
(TA)
(JITTER)
(TS)
(ORT)
(TOD)
(TDR)
(TD1)
(TD2)
Definition of Terms
Digital data Output delay
Maximum Sampling
Frequency
Minimum Sampling
frequency
Bit Error Rate
Full power input
bandwidth
Small Signal Input
bandwidth
Signal to noise and
distortion ratio
Signal to noise ratio
Total harmonic distortion
Spurious free dynamic
range
Effective Number Of Bits
Differential non linearity
Integral non linearity
Aperture delay
Aperture uncertainty
Settling time
Overvoltage recovery
time
Data ready output delay
Time delay from Data
transition to Data Ready
Time delay from Data
Ready to Data
Performances are guaranteed up to Fs max
Performances are guaranteed for clock frequency higher than Fs min
Probability to exceed a specified error threshold for a sample at maximum specified sampling rate. An error
code is a code that differs by more than ± 32 LSB from the correct code.
Analog input frequency at which the fundamental component in the digitally reconstructed output waveform
has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at Full Scale
–1 dB (–1 dBFS).
Analog input frequency at which the fundamental component in the digitally reconstructed output waveform
has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at Full Scale
–10 dB (–10 dBFS).
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale (–1 dBFS), to the RMS sum
of all other spectral components, including the harmonics except DC.
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all other
spectral components excluding the ten first harmonics.
Ratio expressed in dB of the RMS sum of the first ten harmonic components, to the RMS input signal
amplitude. It may be reported in dBFS (i.e, related to converter Full Scale), or in dBc (i.e, related to input
signal level).
Ratio expressed in dB of the RMS signal amplitude to the RMS value of the highest spectral component
(peak spurious spectral component). The peak spurious component may or may not be a harmonic. It may
be reported in dBFS (i.e., related to converter Full Scale), or in dBc (i.e, related to input signal level).
The Differential Non Linearity for an output code i is the difference between the measured step size of code i
and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL
error specification of less than 1 LSB guarantees that there are no missing output codes and that the transfer
function is monotonic.
The Integral Non Linearity for an output code i is the difference between the measured input voltage at which
the transition occurs and the ideal value of this transition.
INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.
Delay between the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point), and the time
at which (V
Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the
signal at the sampling point.
Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step function is applied
to the differential analog input.
Time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input is reduced to
midscale.
Delay from the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point
of change in the differential output data (zero crossing) with specified load.
Delay from the falling edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point
of change in the differential output data (zero crossing) with specified load.
Time delay between Data transition to output clock (Data Ready). If output clock is in the middle of the Data,
TD1 = Tdata/2
Time delay between output clock (Data Ready) to Data transition. If output clock is in the middle of the Data,
TD2 = Tdata/2.
ENOB
IN,
V
INN
=
) is sampled.
SINAD -1.76 + 20 log (A / FS/2)
----------------------------------------------------------------------------------- -
6.02
Where A is the actual input amplitude and FS
is the full scale range of the ADC under test
EV10AS150A
0954B–BDC–12/09
21