EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 58

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
5.3.2
Driving the EV10AS150A with a Square Wave Differential Cock Input
If the clock input signal is a square wave, the incoming signal slew-rate becomes independent to signal
amplitude and frequency:
So far the slew-rate of the square clock signals is constant and controlled (> 5 GV/s), the SNR perfor-
mance of the ADC will be independent to clock signal frequency and amplitude.
Consequently with square wave clock signals, much lower signal amplitudes and frequencies can be
entered to the ADC as with sinewaves. With square waves, the SNR performance will be mainly depen-
dant on time domain jitter, which shall remain below 100 fs rms, to ensure optimum SNR performance
nd
rd
especially in the 2
and 3
Nyquist as detailed in the previous sections.
With a square wave clock input, a minimum amplitude of ±125 mV peak = 250 mVpp can be entered
without impact on linearity (SFDR and THD) and SNR. LVDS logic compatible and LVPECL logic com-
patible clock inputs can therefore be used to drive the EV10AS150A ADC clock input, so far the time
domain jitter of the square wave is < 100 fs rms, and slew-rate is < 5GV/s. So it is not actually the rise/fall
time of the square wave clock signals which are of interest, but the actual Slew-rate of the clock edges.
For LVPECL square wave clock input featuring a typical rise time (20% to 80%) of 75 ps for 800 mV volt-
age swing, the corresponding signal slew-rate is roughly 500 mV/75 ps = 6.6 GV/s, which is convenient.
In addition to that, the time domain jitter shall be < 100 fs rms. (e.g.: 70 fs rms).
LVDS and/or LVPECL compatible low jitter regeneration signals Buffers are commercially available, fea-
turing less than 100 fs rms time domain jitter.
Of course, the sinewave to square wave regeneration buffers shall be driven by a low phase noise sine-
wave reference clock source (> 155 dBc/Hz), as stated in the previous sections:
The additional jitter due to the square wave regeneration circuitry has then to be RSS summed to the
driving sinewave signal time domain jitter (e.g.: 100 fs rms time domain jitter which are achieved by a
155 dBc/Hz sinewave clock source will have to be RSS summed with a 70 fs rms square wave jitter,
2
2
yielding to SQRT(100
+ 70
) = 122 fs rms total external jitter (sinewave & square wave).
In these conditions, the SNR performance of the ADC will be nearly 49 dB at Fin = 3000 MHz, (–1 dBFS
at 2.5 Gsps). It is reminded that an SNR of 50 dB at (3000 MHz, –1 dBFS) is achieved if the external
clock source jitter contribution can be neglected, only taking into account the 120 fs rms intrinsic sam-
pling clock jitter of the ADC, assuming ideal (jitter-free) external clock sources with ultra fast slew-rates
(> 10 GV/s).
Note 1: ADC Minimum sampling clock frequency:
The square wave clock input frequency shall not be lower than 500 MHz minimum, to avoid SNR and
THD rolloff due to front-end Track and Hold droop rate. Recommended minimum value for clock fre-
quency over temperature is 1 GHz to avoid any roll-off in dynamic performance.
Note 2: ADC SNR performance at low analog input frequencies:
The sampling clock jitter effect on SNR is negligible at low input frequencies (oversampling conditions).
The SNR performance for low input frequencies is mainly dictated by the ADC front-end Track and Hold
input referred thermal noise integrated over the 5 GHz Analog input Bandwidth (times π/2 assuming 1
st
order rolloff).
The measured SNR in oversampling conditions is 54 dB.
The ADC deviation from ideal quantification noise (Differential Non Linearity: DNL) on SNR performance
is negligible compared to input referred thermal noise:
st
nd
The measured Differential Non Linearity (DNL) is < 0.5 LSB peak (= 0.2 lsb rms) at 2.5 Gsps 1
and 2
Nyquist, which is the same order of magnitude as quantification noise Q/SQRT(12).
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e2v semiconductors SAS 2009