EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 59

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

5.4
e2v semiconductors SAS 2009
LVDS Output Implementation
Note 3: Effect of 3WSI SDA (Sampling Delay Adjust) tunable delay line on ADC intrinsic jitter
The previous assumptions are made with ADC intrinsic clock jitter = 120 fs rms, which is assuming the
sampling clock adjust is de-activated (SDA OFF), which is the case by default setting at ADC Reset.
If multiple ADCs need to be interleaved, the respective Aperture delays of the ADCs need to be carefully
aligned, and fine tuned with the “SDA” function monitored by the 3 Wire Serial Interface (3WSI), by acti-
vating the SDA function (SDA ON).
Turning “ON” the SDA will activate an internal tunable delay line in serial with the sampling clock path,
(which is bypassed if SDA is turned OFF). By turning ON the SDA, the ADC intrinsic jitter becomes 150
fs rms (with minimum delay), since some additional extra delay cells will contribute to jitter, which will
slightly impact the SNR performance by 1 dB at Fin = 2500 MHz. (50 dB with SDA turned OFF, and 49
dB if SDA is turned ON). If SDA is turned ON and fully tuned (maximum delay), the ADC intrinsic jitter
becomes 170 fs rms.
Refer to chapter 4.6.6. for more information about Sampling Delay Adjust function.
Output Data, Output Clock (Data Ready) and out-of-range bit are LVDS signals that needs to be 100Ω
differentially terminated.
Output data:
A0, B0, C0, D0 are the LSB, A9, B9, C9, D9 are the MSB
Output Clock (Data Ready)
Out of Range
Each of these outputs should be terminated by 100Ω differential resistor placed as close as possible to
the differential receiver (inside receiver is even better).
In 1:2 DMUX Ratio the unused Output Data and out-of-range bit (Port C and D) could be leave floating
without 100Ω differential resistor.
• In-phase (Ai) and inverted phase (AiN) digital outputs on DEMUX Port A (with i = 0…9)
• In-phase (Bi) and inverted phase (BiN) digital outputs on DEMUX Port B (with i = 0…9)
• In-phase (Ci) and inverted phase (CiN) digital outputs on DEMUX Port C (with i = 0…9)
• In-phase (Di) and inverted phase (DiN) digital outputs on DEMUX Port D (with i = 0…9)
• In-phase DR and inverted phase DRN.
• In-phase DRA and inverted phase DRAN on DEMUX Port A used in staggered mode.
• In-phase DRB and inverted phase DRBN on DEMUX Port B used in staggered mode.
• In-phase DRC and inverted phase DRCN on DEMUX Port C used in staggered mode.
• In-phase DRD and inverted phase DRDN on DEMUX Port D used in staggered mode.
• In-phase AOR and inverted phase AORN on DEMUX Port A used in simultaneous mode.
• In-phase BOR and inverted phase BORN on DEMUX Port B used in simultaneous mode.
• In-phase COR and inverted phase CORN on DEMUX Port C used in simultaneous mode.
• In-phase DOR and inverted phase DORN on DEMUX Port D used in simultaneous mode.
EV10AS150A
0954B–BDC–12/09
59