EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 14

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
Table 2-10.
Notes:
2.6
2.6.1
2.6.2
14
Parameter
Minimum Clock pulse width (High)
Minimum Clock pulse width (Low)
External clock Duty cycle
Aperture Delay
Aperture Jitter added by the ADC
Output Rise/Fall time for Data (20% – 80%)
Output Rise/Fall time for Output Clock (20% – 80%)
Digital Data Output propagation delay
Data Ready Clock Output propagation delay
Differential propagation delay (Output Data vs. Data clock)
Tskew (40 digital output data)
Output Data Pipeline delay (Latency)
Synchronized 1:2 mode on Port A
Synchronized 1:2 mode on Port B
Synchronized 1:4 mode on Port A
Synchronized 1:4 mode on Port B
Synchronized 1:4 mode on Port C
Synchronized 1:4 mode on Port D
Staggered 1:2 mode or 1:4 mode
ASYNCRST minimum pulse width
DRR minimum pulse width
1. ADC performance are given for optimum value of 50% external clock duty cycle.
2. ADC Aperture delay and Aperture jitter measured with SDA = OFF. (Default setting at Reset).
3. Rise time and fall time are defined for 100Ω differentially terminated output load with 2nH and 2 pF termination parasitics.
Timing Diagram
0954B–BDC–12/09
Aperture Delay
Latency (Simultaneous Mode and Staggered Mode)
(2)
Switching characteristics (Continued)
The analog input is sampled on the rising edge of the differential clock input (CLK, CLKN) after TA (aper-
ture delay) of +350 ps typical. Aperture delay (TA) is measured at package input balls with the
assumption that the external trace length of analog input and clock input are well matched (6.6 ps/mm of
mismatch with ε
In simultaneous output mode with 1:4 DMUX Ratio, the digitized digital output data N, N+1,N+2, N+3
respectively on port A, B, C and D are aligned (on the latest data available N+3 on port D). The data N
on port A is available after 7.5 Clock cycles pipeline delay, plus an additional propagation delay TOD
(due to Output Buffers + Package propagation delay). Due to data alignment, the pipeline delay is
decreased of one clock cycle for each port from port A to D leading to:
(1)
(2)
r
= 4).
(3))
(3)
Test Level
4
4
4
4
4
4
4
4
4
4
4
4
5
5
TOD – TDR
DRRPW
Symbol
RSTPW
DCYC
TR/TF
TR/TF
Tskew
Jitter
TOD
TDR
TC1
TC2
PD
TA
Min
300
0.2
0.2
45
0
120/120
120/120
± 15
Typ
350
120
150
2.3
2.3
5.5
4.5
7.5
6.5
5.5
4.5
4.5
3.5
50
3
e2v semiconductors SAS 2009
180/180
180/180
Max
± 25
400
200
1.0
1.0
55
Cycles
fs rms
Clock
Unit
ns
ns
ps
ps
ps
ns
ns
ps
ps
ns
ns
%