AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 970

• Manufacturer Part Number: AT32UC3C0512CAU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0512CAU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.6.2.2
32117C–AVR-08/11
Comparator
The comparator continuously compares its counter value with the channel period defined by
CPRD in the
CDTY in the
OCx accordingly.
The different properties of the waveform of the output OCx are:
• the clock selection. The channel counter is clocked by one of the clocks provided by the
• the waveform period. This channel parameter is defined in the CPRD field of the CPRDx
• the waveform duty-cycle. This channel parameter is defined in the CDTY field of the CDTYx
clock generator described in the previous section. This channel parameter is defined in the
CPRE field of the
register.
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM internal clock (CCK) divided by an X given prescaler value (with X being 1,
2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using the PWM internal clock (CCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM internal clock (CCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using the PWM internal clock (CCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
(
------------------------------ -
(
----------------------------------------- -
(
---------------------------------------- -
(
--------------------------------------------------- -
X CPRD
CRPD
2
2
duty cycle
×
×
×
duty cycle
CCK
X CPRD
CPRD DIVA
CCK
CCK
×
CCK
×
DIVA
”Channel Duty Cycle Register” on page 1037
”Channel Period Register” on page 1039
)
×
=
)
)
=
or
(
------------------------------------------------------------------------------------------------------- -
period 1 fchannel_x_clock
(
---------------------------------------------------------------------------------------------------------------------- -
)
(
”Channel Mode Register” on page 1035
period 2 ⁄
or
(
----------------------------------------- -
CRPD DIVB
(
--------------------------------------------------- -
2 CPRD
–
×
CCK
×
⁄
) 1 fchannel_x_clock
CCK
–
×
period
⁄
)
(
DIVB
period 2 ⁄
)
)
×
CDTY
×
(CPRDx) and the duty-cycle defined by
CDTY
)
(CDTYx) to generate an output signal
(CMRx). This field is reset at 0.
) )
AT32UC3C
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