AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 1053

• Manufacturer Part Number: AT32UC3C0512CAU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0512CAU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

34.6.2.2
34.6.2.3
34.6.2.4
32117C–AVR-08/11
Capture register
Glitch filter
Timer/Counter mode
The capture function saves the QDEC counter value in the Capture register (CAP) when a cap-
ture event has occurred. The capture function is enabled if the QDEC counter is running.
The CAP register will not be updated with a new value if the previous value has not been read. If
a capture event occurs and the previous value has not been read, the SR.OVR bit is set.
The QDEC inputs (QEPA/QEPB/QEPI) are passed through a glitch filter that is enabled by writ-
ing a one to the CF.FILTEN bit. The input sent to the QDEC counter will toggle if the input is
stable for three CLK_QDEC_INT periods.
QDEC can be used as a 32-bit/counter with compare/capture capabilities. This timer includes an
up/down (UPD) mode where the timer counts up or down according to a toggle direction event
from the PEVC.
The timer/counter is available by writing a zero to the CF.QDEC bit. Timer/Counter mode uses
the same resources as QDEC mode:
It does not use the input filters and the index pulse control.
The timer/counter includes an up/down mode that is enabled by writing a one to the CF.UPD bit.
• The CNT QDEC counter
• The TOP register to reload the CNT value
• The CMP register to generate a compare peripheral event/interrupt
• The CAP register to save the CNT value in case of a capture peripheral event occurs
• The clock selection
• The trigger mechanism
AT32UC3C
1053