AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 1178

• Manufacturer Part Number: AT32UC3C0512CAU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0512CAU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

38.6.6
38.6.7
32117C–AVR-08/11
Interrupts
Using the Peripheral DMA Controller
To make the CPU able to do other things while waiting for the aWire UART user interface to fin-
ish its operations the aWire UART user interface supports generating interrupts. All status bits in
the Status Register can be used as interrupt sources, except the SR.BUSY and SR.CENABLED
bits.
To enable an interrupt the user must write a one to the corresponding bit in the Interrupt Enable
Register (IER). Upon the next zero to one transition of this SR bit the aWire UART user interface
will flag this interrupt to the CPU. To clear the interrupt the user must write a one to the corre-
sponding bit in the Status Clear Register (SCR).
Interrupts can be disabled by writing a one to the corresponding bit in the Interrupt Disable Reg-
ister (IDR). The interrupt Mask Register (IMR) can be read to check if an interrupt is enabled or
disabled.
To relieve the CPU of data transfers the aWire UART user interface support using the Peripheral
DMA controller.
To transmit using the Peripheral DMA Controller do the following:
To receive using the Peripheral DMA Controller do the following:
1. Setup the aWire UART user interface in transmit mode.
2. Setup the Peripheral DMA Controller with buffer address and length, use byte as trans-
3. Enable the Peripheral DMA Controller.
4. Wait until the Peripheral DMA Controller is done.
1. Setup the aWire UART user interface in receive mode
2. Setup the Peripheral DMA Controller with buffer address and length, use byte as trans-
3. Enable the Peripheral DMA Controller.
4. Wait until the Peripheral DMA Controller is ready.
fer size.
fer size.
AT32UC3C
1178