AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 277
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AT32UC3C0512CAU
Manufacturer Part Number
AT32UC3C0512CAU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3A0128AU.pdf
(2 pages)
4.AT32UC3C0128C.pdf
(1313 pages)
5.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512CAU
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128AU PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- AT32UC3C0128C PDF datasheet #5
- Current page: 277 of 1313
- Download datasheet (20Mb)
15.9.3
15.9.3.1
Table 15-13. User Page Fuse Description
• SS_ADRR: Size of the CPU RAM controlled by the Secure State
• SS_ADRF: Size of the Flash controlled by the Secure State
• WDTDISRV: WatchDog Timer auto disable at startup
15.9.4
32117C–AVR-08/11
WDTDISRV
31
23
15
7
The section of the CPU RAM controlled by the Secure State is from address 0x00000000 to address (SS_ADRR << 10).
The section of the Flash controlled by the Secure State is from address 0x80000000 to address (SS_ADRF << 10).
0: The WDT is automatically enabled at startup, the WDTAUTO fuse of the WDT is set.
1: The WDT is not automatically enabled at startup, the WDTAUTO fuse of the watchdog timer is not set.
Please refer to the WDT chapter for detail about time-out settings when the WDT is automatically enabled.
Fuses in User Page (address 0x80800000)
Bootloader Configuration
First word (address 0x80800000)
30
22
14
6
The devices are shipped with the User page erased (all bits 1).
The USB/USART bootloader uses two words in the flash user page to store its configuration:
Please refer to the bootloader documentation for more information.
• Configuration word 1 at address 0x808001FC is read first at boot time to know if it should
• Configuration word 2 at address 0x808001F8 stores the I/O conditions that determine which
start the ISP process unconditionally and whether it should use the configuration word 2
where further configuration is stored.
of the USB DFU ISP and the application to start at the end of the boot process.
29
21
13
5
28
20
12
4
SS_ADRF[15:8]
SS_ADRR[7:0]
SS_ADRF[7:0]
SS_ADRR[14:8]
27
19
11
3
26
18
10
2
25
17
9
1
AT32UC3C
24
16
8
0
277
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