AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 953

• Manufacturer Part Number: AT32UC3C0512CAU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0512CAU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• DTSEQ: Data Toggle Sequence
• RXSTALLDI: Received STALLed Interrupt
• CRCERRI: CRC Error Interrupt
• ERRORFI: Errorflow Interrupt
• NAKEDI: NAKed Interrupt
• PERRI: Pipe Error Interrupt
• TXSTPI: Transmitted SETUP Interrupt
• TXOUTI: Transmitted OUT Data Interrupt
• RXINI: Received IN Data Interrupt
32117C–AVR-08/11
This field indicates the data PID of the current bank.
For OUT pipes, this field indicates the data toggle of the next packet that will be sent.
For IN pipes, this field indicates the data toggle of the received packet stored in the current bank.
This bit is cleared when the RXSTALLDIC bit is written to one.
This bit is set, for all endpoints (except isochronous), when a STALL handshake has been received on the current bank of the
pipe. The pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one.
This bit is cleared when the CRCERRIC bit is written to one.
This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the pipe. This triggers an interrupt if
the TXSTPE bit is one.
This bit is cleared when the ERRORFIC bit is written to one.
This bit is set:
- for isochronous and interrupt IN/OUT pipes, when an error flow occurs. This triggers an interrupt if the ERRORFIE bit is one.
- for isochronous or interrupt OUT pipes, when a transaction underflow occurs in the current pipe. i.e, the pipe can’t send the
OUT data packet in time because the current bank is not ready.
- for isochronous or interrupt IN pipes, when a transaction flow error occurs in the current pipe. i.e, the current bank of the pipe
is not free when a new IN USB packet is received. This packet is not stored in the bank. For interrupt pipes, the overflowed
packet is ACKed to respect the USB standard.
This bit is cleared when the NAKEDIC bit is written to one.
This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one.
This bit is cleared when the PERRIC bit is written to one.
This bit is set when an error occurs on the current bank of the pipe. This triggers an interrupt if the PERRE bit is set. Refers to
the
This bit is cleared when the TXSTPIC bit is written to one.
This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled. This triggers an interrupt if the
TXSTPE bit is one.
This bit is cleared when the TXOUTIC bit is written to one.
This bit is set when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is one.
This bit is cleared when the RXINIC bit is written to one.
This bit is set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if the RXINE bit is
one.
0
0
1
1
PERSTA structure of the pipe descriptor (
DTSEQ
0
1
0
1
Data toggle sequence
Data0
Data1
reserved
reserved
Figure
32-9) to determine the source of the error.
AT32UC3C
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