AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 1267

• Manufacturer Part Number: AT32UC3C0512CAU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0512CAU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

40.9
40.9.1
Table 40-44. Maximum Reset and Wake-up Timing
32117C–AVR-08/11
Parameter
Startup time from power-up, using
regulator
Startup time from reset release
Wake-up
Timing Characteristics
Startup, Reset, and Wake-up Timing
Idle
Frozen
Standby
Stop
Deepstop
Static
The startup, reset, and wake-up timings are calculated using the following formula:
Where
clock the startup time of the oscillator,
stop, deepstop, and static sleep modes. Please refer to the source for the CPU clock in the
”Oscillator Characteristics” on page 1254
t
t
CPU
=
t
CONST
t
is the period of the CPU clock. If another clock source than RCSYS is selected as CPU
CONST
VDDIN_5 rising (10 mV/ms)
Time from V
the decode stage of CPU. VDDCORE is supplied by
the internal regulator.
Time from releasing a reset source (except POR,
BOD18, and BOD33) to the first instruction entering
the decode stage of CPU.
From wake-up event to the first instruction entering
the decode stage of the CPU.
Measuring
+
N
and
CPU
×
N
CPU
VDDIN_5
t
CPU
are found in
=0 to the first instruction entering
t
Table
OSCSTART
for more details about oscillator startup times.
40-44.
, must be added to the wake-up time in the
t
CONST
Max
268+
268+
268+
is the delay relative to RCSYS,
t
CONST
t
t
t
2600
1240
OSCSTART
OSCSTART
OSCSTART
268
268
0
(in µs)
AT32UC3C
Max
209
209
212
212
212
N
19
0
0
CPU
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