AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 937
AT32UC3C0512CAU
Manufacturer Part Number
AT32UC3C0512CAU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3A0128AU.pdf
(2 pages)
4.AT32UC3C0128C.pdf
(1313 pages)
5.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512CAU
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128AU PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- AT32UC3C0128C PDF datasheet #5
- Current page: 937 of 1313
- Download datasheet (20Mb)
•
• NBUSYBKE: Number of Busy Banks Interrupt Enable
• RAMACERE: RAMACER Interrupt Enable
• STALLEDE: STALLed Interrupt Enable
• CRCERRE: CRC Error Interrupt Enable
• NAKINE: NAKed IN Interrupt Enable
• NAKOUTE: NAKed OUT Interrupt Enable
• RXSTPE: Received SETUP Interrupt Enable
• ERRORFE: Errorflow Interrupt Enable
• RXOUTE: Received OUT Data Interrupt Enable
• TXINE: Transmitted IN Data Interrupt Enable
32117C–AVR-08/11
KILLBK: Kill IN Bank
This bit is cleared by hardware after the completion of the “kill packet procedure”.
This bit is set when the KILLBKS bit is written to one, killing the last written bank.
The user shall wait for this bit to be cleared before trying to process another IN packet.
Caution: The bank is cleared when the “kill packet” procedure is completed by the USBC core:
If the bank is really killed, the NBUSYBK field is decremented.
If the bank sent instead of killed (IN transfer), the NBUSYBK field is decremented and the TXINI flag is set. This specific case
Note: If two banks are ready to be sent, the above specific case will not occur, since the first bank is sent (IN transfer) while the
This bit is cleared when the NBUSYBKEC bit is written to zero, disabling the Number of Busy Banks interrupt (NBUSYBK).
This bit is set when the NBUSYBKES bit is written to one, enabling the Number of Busy Banks interrupt (NBUSYBK).
This bit is cleared when the RAMACEREC bit is written to one, disabling the RAMACER interrupt (RAMACERI).
This bit is set when the RAMACERES bit is written to one, enabling the RAMACER interrupt (RAMACERI).
This bit is cleared when the STALLEDEC bit is written to one, disabling the STALLed interrupt (STALLEDI).
This bit is set when the STALLEDES bit is written to one, enabling the STALLed interrupt (STALLEDI).
This bit is cleared when the CRCERREC bit is written to one, disabling the CRC Error interrupt (CRCERRI).
This bit is set when the CRCERRES bit is written to one, enabling the CRC Error interrupt (CRCERRI).
This bit is cleared when the NAKINEC bit is written to one, disabling the NAKed IN interrupt (NAKINI).
This bit is set when the NAKINES bit is written to one, enabling the NAKed IN interrupt (NAKINI).
This bit is cleared when the NAKOUTEC bit is written to one, disabling the NAKed OUT interrupt (NAKOUTI).
This bit is set when the NAKOUTES bit is written to one, enabling the NAKed OUT interrupt (NAKOUTI).
This bit is cleared when the RXSTPEC bit is written to one, disabling the Received SETUP interrupt (RXSTPI).
This bit is set when the RXSTPES bit is written to one, enabling the Received SETUP interrupt (RXSTPI).
This bit is cleared when the ERRORFEC bit is written to one, disabling the Underflow interrupt (ERRORFI).
This bit is set when the ERRORFES bit is written to one, enabling the Underflow interrupt (ERRORFI).
This bit is cleared when the RXOUTEC bit is written to one, disabling the Received OUT Data interrupt (RXOUT).
This bit is set when the RXOUTES bit is written to one, enabling the Received OUT Data interrupt (RXOUT).
This bit is cleared when the TXINEC bit is written to one, disabling the Transmitted IN Data interrupt (TXINI).
This bit is set when the TXINES bit is written to one, enabling the Transmitted IN Data interrupt (TXINI).
can occur if an IN token comes while the user tries to kill the bank.
last bank is killed.
AT32UC3C
937
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