AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 138

• Manufacturer Part Number: AT32UC3C0512CAU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0512CAU

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.5.3.2
9.5.4
32117C–AVR-08/11
Peripheral events
Alarm interrupt
prescaler when the AST is enabled. The bit is selected by the Interval Select field in the corre-
sponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of
where f
The corresponding PERn bit in the Status Register (SR) will be set when the selected bit in the
prescaler has a 0-to-1 transition.
Because of synchronization, the transfer of the INSEL value will not happen immediately. When
changing/setting the INSEL value, the user must make sure that the prescaler bit number INSEL
will not have a 0-to-1 transition before the INSEL value is transferred to the register. In that case,
the first periodic interrupt after the change will not be triggered.
The AST can also generate alarm interrupts. If the ALARMn bit in IMR is one, the AST will gen-
erate an interrupt request when the counter value matches the selected alarm value, when the
AST is enabled. The alarm value is selected by writing the value to the VALUE field in the corre-
sponding Alarm Register (ARn.VALUE).
The corresponding ALARMn bit in SR will be set when the counter reaches the selected alarm
value.
Because of synchronization, the transfer of the alarm value will not happen immediately. When
changing/setting the alarm value, the user must make sure that the counter will not count the
selected alarm value before the value is transferred to the register. In that case, the first alarm
interrupt after the change will not be triggered.
If the Clear on Alarm bit in the Control Register (CR.CAn) is one, the corresponding alarm inter-
rupt will clear the counter and set the OVF bit in the Status Register. This will generate an
overflow interrupt if the OVF bit in IMR is set.
The AST can generate a number of peripheral events:
The PERn peripheral event(s) is generated the same way as the PER interrupt, as described in
Section
interrupt, as described in
as the OVF interrupt, as described in
• OVF
• PER0
• PER1
• ALARM0
• ALARM1
CS
9.5.3.1. The ALARMn peripheral event(s) is generated the same way as the ALARM
is the frequency of the selected clock source.
Section
9.5.3.2. The OVF peripheral event is generated the same way
Section
f
PA
=
9.5.3-
------------------------ -
2
INSEL
f
CS
+
1
AT32UC3C
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