LSISASX12 LSI, LSISASX12 Datasheet - Page 99

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4028
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
TE
TLV
This register controls the API2C t
that the master controller extends the SCL signal LOW during the
transmission or reception of a data byte.
R
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Load value = Desired Time-Out/Divided Clock Period
Reserved
These bits are reserved.
Timer Enable
This bit enables the API2C t
TE
0
1
Timer Load Value
This value loads into the timer if the timer is enabled, and
if the SCL signal is detected LOW following a HIGH
value. The timer counts down from this value at the
divided clock rate. If the timer reaches 0, the device sets
the time-out flag. Following a time-out, the timer reloads
the Timer Load Value when the SCL signal is detected
LOW again following a HIGH state.
The software programs this value for a certain time-out
period, depending on the APB clock frequency, and
according to the following formula:
Reserved
These bits are reserved.
API2C tLOW Control
Function
Disables timer and forces API2C t
Enables the t
16 15
LOW
TIMEOUT
timer. This timer measures the time
timer.
TIMEOUT
8 7
0
timer.
TIMEOUT
0 0 0 0
flag to 0.
[31:16]
[31:16]
[14:0]
0
4-21
15
0
0