LSISASX12 LSI, LSISASX12 Datasheet - Page 137

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0xC010
Read/Write
Register: 0xC014
Read/Write
31
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The SIO Output Data Control registers provide data output control for
PHY[11:0]. Each SIO Output Data register uses one of two possible bit
field definitions. One bit field definition provides the bit definitions for the
standard SGPIO mode; the other bit field definition provides the bit
definitions for the enhanced SGPIO mode only available on the
LSISASx12A.
Each byte of this register generates 3 serialized I/O bits on the SioDout
line. This register controls SIO bits [11:0], which are for devices 3 through
0.
The following are the bit definitions for standard SIO mode:
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
24 23
SIO General Purpose Receive 1
Reserved
SIO General Purpose Receive 0
When the SIO Device Count is set to 10 or 11, bit 0 of
this register contains bit 32 from the SioDin line and bits
[3:1] of this register are reserved. When SIO Device
Count is set to 11, bits [3:0] of this register contain bits
[35:32] from the SioDin line.
SIO Output Data Control 0
SIO bit 11: Error Device 3
16 15
16 15
8 7
8 7
0
0
0 0 0 0
0 0 0 0
[31:29]
[31:4]
0
0
[3:0]
4-59
0
0
0
0