LSISASX12 LSI, LSISASX12 Datasheet - Page 175

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x0028
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4.9
This register provides test control signals. These controls are not used
during normal operation.
SPhynx Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Select Pattern Description
0,7
1
2
3
4
5
6
CJTPAT Jitter patter from SAS Annex A
ALIGN Transmit 6 ALIGN0 frames for synchronization before the jitter
COMP SATA Composite of patterns 2–5
HRQR SATA Half-rate/Quarter-rate High Transaction Density Pattern
SSOP SATA Simultaneous Switching Outputs Pattern
LFSC SATA Low Frequency Spectral Content Pattern
LTDP SATA Low Transaction Density Pattern
Jitter Pattern Selection
test
Reserved
RX Jitter Enable
Setting this bit enables receive jitter pattern checking.
TX Jitter Enable
Setting this bit enables transmit jitter pattern generation.
JPAT Select
This field specifies the jitter pattern for transmit genera-
tion and receive checking.
ing for this field.
Test Register
16 15
Table 4.9
8 7
provides the encod-
0
0 0 0 0
[31:13]
[10:8]
0
4-97
12
11
0
0