LSISASX12 LSI, LSISASX12 Datasheet - Page 102

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4048
Read/Write
4-24
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCLC
SDAS
SCLS
This register allows the host to independently reset the API2C interface.
R
I2CR
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
SCL Control
This bit controls the SCL signal.
SCLC
0
1
SDA Status
This bit reflects the current synchronized and filtered
value of the SDA signal on the API2C interface. This bit
is read only.
SCL Status
This bit reflects the current synchronized and filtered
value of the SCL signal on the API2C interface. This bit
is read only.
Reserved
These bits are reserved.
API2C Reset
Setting this bit resets the API2C module. This bit clears
automatically when the reset completes. The reset:
Forces all master state machines to their IDLE states
Insures that the API2C core is not driving the API2C
interface
Clears the Master Enable bit in the
Control
Clears master status bits
API2C Soft Reset
Function
interface.
16 15
SCL is not forced LOW.
SCL is forced LOW on the API2C
register
8 7
0
API2C Global
0 0 0 0
[31:1]
0
0
0
2
1
0
0