LSISASX12 LSI, LSISASX12 Datasheet - Page 100

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4038
Read/Write
4-22
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE
TLV
The following register divides the APB clock frequency to use for all of
the timers. The value in the register picks a power of two value from a
free running 16-bit counter that serves as an enable for the timers.
R
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Load value = Desired Time-Out/Divided Clock Period
API2C Timer Clock Divider Control
Timer Enable
This bit enables the API2C t
TE
0
1
API2C Timer Load Value
This value loads into the timer at the beginning of every
data byte transfer to or from the API2C interface (Start or
ACK of previous byte). When the timer is enabled and the
master controller extends the SCL signal by asserting the
SCL hold signal, the timer counts down from the timer
value at the divided clock rate. If the timer reaches 0, the
device sets the time-out flag. Following a time-out, the
timer reloads the Timer Load Value at the beginning of
the next data byte transfer.
The software programs this value for a certain time-out
period, depending on the APB clock frequency, and
according to the following formula:
Reserved
These bits are reserved.
Function
The timer is disabled and the API2C t
forced to 0.
The t
16 15
LOW
timer is enabled.
LOW
8 7
timer.
0
0 0 0 0
LOW
flag is
[14:0]
[31:4]
0
15
0
0