LSISASX12 LSI, LSISASX12 Datasheet - Page 176

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x0034
Read/Write
4-98
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides status signals to observe during testing. It is not
for use during normal operation.
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Force Data Rate
When set, this field overrides the minimum and maximum
data rate settings for the phy layer. The data rate selected
in this field applies to both the receivers and transmitters.
The encodings of this field are
Encoding
0b1000
0b1001
All others encodings of this field are reserved.
Force SATA
Setting this bit causes the LSISASx12 to report as a
SATA device. Use this bit in conjunction with the Bypass
Reset Sequence bit.
Select Starting Disparity
This bit selects the starting disparity to be transmitted in
the encoder when the LSISASx12 transitions from IDLE.
Clearing this bit indicates negative disparity. Setting this
bit indicates positive disparity.
Bypass Reset Sequence
Setting this bit causes the LSISASx12 to bypass the nor-
mal OOB reset sequence, and to use the rate set in the
Force Data Rate field as the negotiated rate.
Reserved
Reserved
Custom Jitter
16 15
Definition
1.5 Gbits/s
3.0 Gbits/s
8 7
0
0 0 0 0
[31:20]
0
[7:4]
0
0
3
2
1
0