LSISASX12 LSI, LSISASX12 Datasheet - Page 213

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

EMB Slave Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Link/Device Reset Received
This bit indicates that the LSISASx12 detected either a
link reset from an SMP PHY CONTROL (Link/Hard
Reset) Request Frame or received a DEVICE RESET
command. The SEP aborts the current operation and
sets a flag to indicate a UNIT ATTENTION condition.
Write this bit once to clear it. The SEP also sets the SEP
Aborted Command bit in the
Read Data Transmitted
This bit is an acknowledgement to the Read Data Ready
bit of the SEP-STP Doorbell register. It indicates that the
STP Target has transferred the data from the Data FIS
RAM to the host. Write this bit once to clear it.
Write Data Ready
This bit indicates that there is valid write data in the Data
FIS RAM to transfer to the SEP. Write this bit once to
clear it.
Soft Reset Sequence Received
This bit indicates that the LSISASx12 detected a soft
reset sequence. The SEP must abort any command
under execution and runs diagnostic tests. Upon comple-
tion of the diagnostic tests, the SEP must write the
results to the Command Status register. A value of 0x00
indicates that the diagnostics tests failed. A value of 0x01
indicates that the diagnostics tests passed. The SEP also
must set a UNIT ATTENTION flag when this bit is set.
Identify Packet Device Command Received
This bit indicates that an Identify Packet Device Com-
mand was received. The SEP transfers the 512 bytes of
response data to the Data FIS RAM and sets the Read
Data Ready bit of the SEP-STP Doorbell register. Write
this bit once to clear it.
command and reconnected to send a Device Reset
command.
The STP Target tried to re-establish a connection by
sending an OAF, and either received an OPEN
Timeout or a fatal OPEN_REJECT primitive, such as
NO DESTINATION and WRONG DESTINATION.
SEP - STP Doorbell
register.
4-135
5
4
3
2
1