LSISASX12 LSI, LSISASX12 Datasheet - Page 97

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4010
Read/Write
Register: 0x4018
Read/Write
31
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register enables the reporting of interrupt status for the master
interrupt sources. The status is reported through the corresponding
API2C Interrupt Status
signal.
R
MIE
This register controls the wait timer. The wait timer times API2C
transactions and causes the appropriate state machine to take action
when a time-out occurs.
R
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
24 23
Reserved
These bits are reserved.
Master Interrupt Enable
This bit enables the master interrupt status.
MIE
0
1
Reserved
These bits are reserved.
API2C Wait Timer Control
API2C Interrupt Enable
Function
The reporting of the master interrupt is disabled.
The master interrupt is enabled. A master interrupt
sets the master interrupt status bit and asserts the
master contribution to the external IRQ signal if one
or more of the master interrupt sources are true.
16 15
16 15
register bit and through the external interrupt
8 7
8 7
0
0
0 0 0 0
0 0 0 0
[31:16]
[31:1]
0
0
4-19
0
0
0
0
0