LSISASX12 LSI, LSISASX12 Datasheet - Page 13

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Tables
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
5.1
5.2
Version 3.0
SIO Signal Description and Mapping
Port Number Encodings
SMP Write N Registers Request Frame
SMP Write N Registers Response Frame
SMP Read N Registers Request Frame
SMP Read N Registers Response Frame
Boot Record Format – Fixed Data Field
SIO Control Select Bit Encoding
Timebase Bit Definition
Expected Doorbells and SATA FISes
SAS/SATA Signal Description
Serial EEPROM Interface Signal Description
I
Configuration and General-Purpose Signal Description
Multiplexed SIO Signals
JTAG and Test Pins Signal Description
Factory Test Pins
Power and Ground Pins
Top-Level Address Map
Configuration Manager Config Register Map
LED Group Configuration Settings
Group Override Pin Operation
SMP Target Register Map
Sphynx Link Register Map
SAS Phy Register Map
Phy Operations Encodings
Jitter Pattern Selection
STP Target Register Map
SmpPhyOp Commands
Connection Manager Phy Offsets
Connection Manager Remote Bank Offsets
Connection Manager Remote Bank Register Map
I
Absolute Maximum Stress Ratings
Operating Conditions
2
2
C and EMB Signal Description
C Slave Register Map
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
4-118
4-124
4-130
4-130
4-133
2-12
2-13
2-15
2-15
2-16
2-19
2-27
2-27
2-34
4-41
4-50
4-72
4-75
4-93
4-94
4-97
4-99
2-8
3-4
3-5
3-5
3-6
3-7
3-8
3-8
3-9
4-2
4-3
5-2
5-2
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