LSISASX12 LSI, LSISASX12 Datasheet - Page 115

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4108
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The programmed High Clock Count value loads into a 16-bit counter at
the start of the master HIGH state. The counter decrements on each
PCLK cycle. When the counter reaches 0, the SCL state machine
transitions to the master LOW state.
R
SHCC
This register sets up the clock based on the 75 MHz PCLK frequency. It
is configured automatically during system initialization. It is not necessary
to program this register.
This register determines the low period for the SCL clock that the API2C
master state machine generates. The value specifies the number of
PCLK cycles that the SCL clock is LOW.
The programmed Low Clock Count value loads into a 16-bit counter at
the start of the master LOW state. The counter decrements on each
PCLK cycle. When the counter reaches 0, the SCL state machine
transitions to the master wait state and releases the SCL signal.
R
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Reserved
These bits are reserved.
SCL High Clock Count
This value loads in the 16-bit SCL timer.
Program an appropriate value for the desired speed
mode. The available modes are the standard mode or the
fast mode. Derive the appropriate value by using the fol-
lowing equation.
Reserved
These bits are reserved.
API2C SCL Low Period
(Desired_SCL_High_Time/PCLK_period) – 1
16 15
8 7
0
0 0 0 0
[31:16]
[31:16]
[15:0]
0
4-37
0
0