LSISASX12 LSI, LSISASX12 Datasheet - Page 116

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4110
Read/Write
4-38
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SLCC
This register sets up the clock based on the 75 MHz PCLK frequency. It
is configured automatically during system initialization. It is not necessary
to program this register.
This register controls the spike filter for SCL and SDA. The filter stages
determine the maximum size of the spike that the filter suppresses. The
number of stages is expressed by the number of PCLK cycles.
R
FS
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
SCL Low Clock Count
This is the value loads in the 16-bit SCL timer.
Program an appropriate value for the desired speed
mode. The available modes are the standard mode or the
fast mode. Derive the appropriate value by using the fol-
lowing equation.
Reserved
These bits are reserved.
Filter Stages
This five-bit value determines the number of spike filter
stages. This is the size of the maximum spike sup-
pressed. The value is in units of PCLK cycles. The max-
imum number of allowable stages is 16. Programming a
value greater than 16 disables the filter, and no filtering
occurs.
API2C Spike Filter Control
(Desired_SCL_Low_Time/PCLK_period) – 1
16 15
8 7
0
0 0 0 0
[15:0]
[31:5]
0
[4:0]
0
0