LSISASX12 LSI, LSISASX12 Datasheet - Page 98

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4020
Read/Write
4-20
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TE
TLV
This register controls the API2C t
time that the SCL signal is detected LOW.
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Load value = Desired Time-Out/Divided Clock Period
Timer Enable
This bit enables the wait timer.
TE
0
1
When the timer is enabled and the master state machine-
extends the SCL LOW time by asserting an internal hold
signal, the Timer Load Value loads into the timer. The
timer then counts down at the divided clock rate.
When the timer reaches 0, the time-out flag is set and
sent to the master state machine. The flag clears when
the master hold signal switches to false or when the timer
is disabled.
Timer Load Value
This 15-bit value loads into the timer if the timer is
enabled, and if the master state machine extends the
SCL LOW time. The timer counts down to 0 at the divided
clock rate. If the timer reaches 0, the time-out flag is set.
Following a time-out, the timer reloads the Timer Load
Value when the timer is enabled and the master causes
the SCL LOW time to extend.
The software programs this value for a certain time-out
period, depending on the APB clock frequency according
to:
API2C tTIMEOUT Control
Function
Disables the timer and forces time-out flag to 0.
Enables the timer.
16 15
TIMEOUT
timer. This timer measures the
8 7
0
0 0 0 0
[14:0]
0
15
0
0