LSISASX12 LSI, LSISASX12 Datasheet - Page 199

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x032C
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
All bits in this register are persistent, and remain set until an SMP PHY
CONTROL (CLEAR ERROR LOG), (HARD RESET), (LINK RESET)
function is issued to Virtual Phy 12.
STP Target Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
R_ERRs Received Count
This read-only field indicates the number of times the
STP Target has received an R_ERR in response to a
transmitted FIS. The value increments when the STP Tar-
get detects an R_ERR primitive.
This register does not increment after reaching the max-
imum value of 0xFFFF. Writing 0x05 to the SmpPhyOp
field in the
ter. Bytes 26
Response Frame report the contents of this register.
Reserved
Unrecovered I
The LSISASx12 sets this read-only bit when an I
error occurs, the SEP I
limit, and the I
I
The LSISASx12 sets this read-only bit when an I
error occurs. The SEP I
Unrecovered Data FIS
The LSISASx12 sets this read-only bit when the STP
Target receives an R_ERR primitive in response to a
Data FIS transmission attempt. If this occurs, the STP
Target transmits a CLOSE sequence to close the
connection if the command was not a PACKET
command. If the failed Data FIS is part of a PACKET
command sequence, the STP Target transmits a D2H
2
C CRC Error
STP Error Status
16 15
SMP Phy Operation
–
27 of the SMP REPORT PHY ERROR LOG
2
2
C master has aborted the command.
C CRC Error
2
2
C master has reached its retry
C master may retry the transfer.
8 7
register clears this regis-
0
0 0 0 0
2
2
C CRC
C CRC
[31:16]
0
4-121
15:0
15
14
13
0
0