ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 98

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
4.8.4 I
A standard I
on four parts: START condition, device slave
address transmission, data transfer and STOP
condition. They are described brielfly in the
following section and illustrated in
more details, refer to the I
4.8.4.1 START condition
When the bus is free (both SCL and SDA lines are
at a high level), a master can initiate a
communication by sending a START signal. This
signal is defined as a high-to-low transition of SDA
while SCL is stable high. The bus is considered to
be busy after a START condition.
This
command for data transfer.
4.8.4.2 Slave Address Transmission
The first byte following a START condition is the
slave address transmitted by the master. This
address is 7-bit long followed by an 8th bit (Least
significant bit: LSB) which is the data direction bit
(R/W bit).
– A “0” indicates a transmission (WRITE) from the
– A “1” indicates a request for data (READ) from
If a slave device is present on the bus at the given
address, an Acknowledge will be generated on the
9th clock pulse.
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master to the slave.
the slave to the master.
SDA
SCL
SDA
SCL
2
START
C BUS Protocol
Start
Start
Device Slave Address
2
Device Slave Address
C communication is normally based
condition
A0h
A1h
2
C bus specification).
Ack
must
Ack
WRITE DATA TO I2C DEVICE (Slave Address A0h)
READ DATA FROM I2C DEVICE (Slave Address A1h)
Data Address
precede
Figure 58
Data1(00h) Ack
00h
any
(for
Ack
4.8.4.3 Data Transfer
Once the slave address is acknowledged, the data
transfer can proceed in the direction given by the
R/W bit sent in the address.
Data is transferred with the most significant bit
(MSB) first. Data bits can be changed only when
SCL is low and must be held stable when SCL is
high.
One complete data byte transfer requires 9 clock
pulses: 8 bits + 1 acknowledge bit.
4.8.4.4 Acknowledge Bit (ACK / NACK)
Every byte put on the SDA line is 8-bit long
followed by an acknowledge bit.
This bit is used to indicate a successful data
transfer. The bus transmitter, either master or
slave, releases the SDA line during the 9th clock
period (after sending all 8 bits of data), then:
– To generate an Acknowledge (ACK) of the cur-
– To generate a No-Acknowledge (NACK) of the
4.8.4.5 STOP Condition
A STOP condition is defined by a low-to-high
transition of SDA while SCL is stable high. It ends
the communication between the Interface and the
bus master.
Figure 58. I
Data1(B0h)
rent byte, the receiver pulls the SDA line low.
current byte, the receiver releases the SDA line
(hence at a high level).
Data2(B0h)
2
Ack
C Signal Diagram
Ack
DataN(F0h) Ack STOP
DataN(F0h) Nack STOP