ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 137

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

AC/DC ELECTRICAL CHARACTERISTICS (Cont’d)
1)The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL
2)The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal
Cb = total capacitance of one bus line in pF
Hysteresis of Schmitt trigger inputs
Fixed input levels
V
Pulse width of spikes which must be sup-
pressed by the input filter
Output fall time from VIH min to VIL max with
a bus capacitance from 10 pF to 400 pF
with up to 3 mA sink current at VOL1
with up to 6 mA sink current at VOL2
Input current each I/O pin with an input voltage
between 0.4V and 0.9 V
Capacitance for each I/O pin
na = not applicable
Cb = capacitance of one bus in pF
Bus free time between a STOP and START con-
dition
Hold time START condition. After this period,
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
the first clock pulse is generated
DD
-related input levels
Parameter
Parameter
DD
max
I2C/DDC-Bus Electrical specifications
I2C/DDC-Bus Timings
Symbol
V
T
T
I
C
SP
OF
HYS
4.7
4.0
4.7
4.0
4.7
0 (1)
250
4.0
Standard I2C
Min
V
ns
ns
pF
Unit
A
1000
300
400
Max
Standard mode I2C
na
na
na
na
- 10
Min
1.3
0.6
1.3
0.6
0.6
0 (1)
100
20+0.1Cb
20+0.1Cb
0.6
Min
ST72774/ST727754/ST72734
na
na
na
250
na
10
10
Fast I2C
Max
0.9(2)
300
300
400
Max
0.2
0,05 V
0 ns
20+0.1C
b
20+0.1C
b
-10
Min
Fast mode I2C
DD
T
T
T
T
T
T
T
T
TF
T
Cb
Symbol
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
SU
:
STO
50 ns
250
250
10
10
Max
137/144
ms
ns
ns
ns
ns
ns
pF
Unit
s
s
s
s