ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 40

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
Table 13. Watchdog Timing (f
Notes: Following a reset, the watchdog is
disabled. Once activated it cannot be disabled,
except by a reset.
The T6 bit can be used to generate a software
reset (the WDGA bit is set and the T6 bit is
cleared).
4.2.4 Interrupts
None.
Table 14. Watchdog Timer Register Map and Reset Values
40/144
Address
Max
Min
(Hex.)
08
Reset Value
CR Register
initial value
Register
WDGCR
Label
C0h
FFh
WDGA
7
0
WDG timeout period
CPU
393.216
= 8 MHz)
6.144
(ms)
T6
6
1
T5
5
1
4.2.5 Register Description
CONTROL REGISTER (CR)
Read /Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit .
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
WDGA
0: Watchdog disabled
1: Watchdog enabled
T4
7
4
1
T6
T3
3
1
T5
T4
T2
2
1
T3
T1
T2
1
1
T1
T0
0
1
T0
0