ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 69

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

SYNC PROCESSOR (SYNC) (Cont’d)
MUX CONTROL REGISTER (MCR)
Read/Write
Reset Value: 0010 0000 (20h)
Bit 7:6 = BP1, BP0 Back Porch Pulse control
Bit 5 = FBSEL VSYNCO/HSYNCO or VFBACK/
HFBACK analysis
Bit 4 = SCI0 HSYNCI/CSYNCI selection
Bit 3:2 = HS1, HS0 Horizontal Signal selection
These bits allow inversion of the HSYNCI/CSYNCI
BP1
BP1
7
0
0
1
1
0: HFBACK & VFBACK
1: HSYNCO & VSYNCO
0: HSYNCI
1: CSYNCI
BP0 FBSEL SCI0 HS1
BP0
0
1
0
1
No Back Porch, Moire output selected
167ns Back Porch ± 10 ns
333ns Back Porch ± 10 ns
666ns Back Porch ± 10 ns
Back Porch pulse width
HS0
VOP
0
-
Note: In case of composite sync, if HSYNCO blanking is
Bit 1 = VOP Vertical Polarity control
The VOP bit inverts the VSYNCO Sync signal.
Note: If at each vertical input capture the VPOL bit is cop-
Note: The internally extracted VSYNCO has ALWAYS
Bit 0 = Reserved. Must always be cleared.
HS1
0
0
1
1
0: No polarity inversion (VSYNC0 <- VSYNCI)
1: Inversion enabled (VSYNC0 <- VSYNCI)
enabled (HINH=0 in the ENR register), HS1 must =
1 (CLAMPOUT after HSYNCO rising edge not al-
lowed).
ied by software on the VOP bit, the VSYNCO signal
will have a constant positive polarity.
negative polarity.
HS0
0
1
0
1
CLAMPOUT after HSYNCO rising edge
HSYNC0 <- (HSYNCI, CSYNCI)
CLAMPOUT after HSYNCO rising edge
HSYNC0 <- (HSYNCI, CSYNCI)
CLAMPOUT after HSYNCO falling edge
HSYNC0 <- (HSYNCI, CSYNCI)
CLAMPOUT after HSYNCO falling edge
HSYNC0 <- (HSYNCI,CSYNCI)
ST72774/ST727754/ST72734
HSYNCI Selection Mode
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