ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 100

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
The Write and Read operations allow the EDID
data to be downloaded during factory alignment
(for example).
Writes to the memory by the DMA engine can be
inhibited by means of the WP bit in the DCR
register.
A write of the last data structure byte sets a flag
and may be programmed to generate an interrupt
request.
The Data address (sub-address) is either the
second byte of write transfers or is pointed to by
the
incremented after each byte transfer.
Physical address mapping of the data structure
within the memory space is performed with a
dedicated register accessible by software.
4.8.5.1.2 Mode description
DDC1 Mode: This mode is only enabled when the
DDC v2 or P&D-DDC v2 standards are validated. It
transmits only the EDID v1 data (128 bytes).
To switch the DDC1/2B Interface to DDC1 mode,
software must first clear the CF0 bit in the DCR
Figure 59. DDC1 Waveforms
100/144
SDA
Vsync
ALR
SDA
Vsync
PE
SCL
ALR
PE
SCL
internal
address
1
Bit 7
counter
2
Bit 6
automatically
7Fh
XX
8
Bit 0
register while the HWPE bit=0 and then set the
HWPE bit to enable the DDC1/2B Interface.
A proper initialization sequence (see
must supply nine clock pulses on the VSYNCI pin
in order to internally synchronize the device.
During this initialization sequence, the SDA pin is
in high impedance. On the rising edge of the 10th
pulse applied on VSYNCI, the device outputs on
SDA the most significant (MSB) bit of the byte
located at data address 00h.
A byte is clocked out by means of 9 clock pulses
on Vsync, 8 clock pulses for the data byte itself and
an extra pulse for a Don’t Care bit.
As long as SCL is not held low, each byte of the
memory array is transmitted serially on SDA.
The internal address counter is incremented
automatically until the last byte is transmitted.
Then, it rolls over to relative location 00h.
The physical mapping of the data structure
depends on the configuration and on the content of
the AHR register which can be set by software
(see
Figure
9
60).
10
Bit 7
Bit 7
00h
00h
11
Bit 6
Bit 6
Figure
59)