ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 60

ST72T774J9B1

Manufacturer Part Number
ST72T774J9B1
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72T774J9B1

Cpu Family
ST7
Device Core Size
8b
Frequency (max)
24MHz
Interface Type
I2C/USB
Program Memory Type
EPROM
Program Memory Size
60KB
Total Internal Ram Size
1KB
# I/os (max)
31
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4V
On-chip Adc
1-chx8-bit
On-chip Dac
1-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
42
Package Type
SPDIP
Lead Free Status / Rohs Status
Specific Sites Compliant

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ST72774/ST727754/ST72734
Figure 41. Moire Output (instead of Clamping Output)
4.4.5.1 Blanking output signal
The Video Blanking function uses VSYNCO,
HFBACK,
BLANKOUT output as Video Blanking Output. This
output pin is a 5V open-drain output and can be
AND-wired with any external video blanking signal.
Note: HFBACK, VFBACK, VSYNCO signals must have
Figure 42. Video Blanking Stage Simplified Schematic
60/144
VFBACK
Moire
HFBACK
HFBACK
VFBACK
VSYNCO
positive polarity.
VFBACK
as
input
To Edge detector (LATR)
To Edge detector (LATR)
signals
R
S
and
To use the video blanking signal:
– Program the polarity:
– Enable the BLANKOUT output:
BLKINV bit in POLR register
BLKEN bit in ENR register
BLKINV
BLKEN
BLANKOUT

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