ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 121

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

PWM/BRM GENERATOR (Cont’d)
4.9.4 Register Description
4.9.4.1 PWM/BRM REGISTERS
On a channel basis, the 10 bits are separated into
two data registers:
– A 6-bit PWM register corresponding to the binary
– A 4-bit BRM register defining the intervals where
Note: The number of PWM and BRM channels available
PWM[1:8] REGISTERS
Read/Write
Reset Value 1000 0000 (80h)
Bit 7 = Reserved (read as “1”)
Bit 6 = POL Polarity Bit.
When POL is set, output signal polarity is inverse;
otherwise, no change occurs.
Bits 5:0 = P[5:0] PWM Pulse Binary Weight for
channel i .
For example (10-bit)
Effective (with external RC filtering) DAC value
weight of the PWM pulse.
an incremental pulse is added to the beginning of
the original PWM pulse. Two BRM channel val-
ues share the same register.
7
1
0
0
depends on the device. Refer to the device pin de-
scription and register map.
POL
POL
POL
P5
P
P4
P
P3
P
P
P2
P
P
P1
P
P0
0
P
P
BRM REGISTERS
BRM21 (Channels 2 + 1)
BRM43 (Channels 4 + 3)
BRM65 (Channels 6 + 5)
BRM87 (Channels 8 + 7)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:4 = B[7:4] BRM Bits (channel i+1)
Bits 3:0 = B[3:0] BRM Bits (channel i)
4.9.4.2 OUTPUT ENABLE REGISTER
Read/Write
Reset Value 1000 0000 (80h)
Bit 7:0 = OE[7:0] Output Enable Bit.
When OEi is set, PWM output function is enabled.
Note: From the programmer’s point of view, the PWM and
OE7
P
B7
0: PWM output is disabled
1: PWM output is enabled
7
7
P
BRM registers can be regarded as being combined
to give one data value.
OE6
B6
P
+
OE5
B5
ST72774/ST727754/ST72734
B
OE4
B4
B
OE3
B3
B
B
OE2
B2
B
B
OE1
B1
121/144
OE0
B
B0
B
0
0