ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 92

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
I
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event
occurs. It is cleared by software reading SR2
register in case of error event or as described in
Figure
interface is disabled (PE=0).
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware when the
interface is disabled (PE=0).
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is
correctly received or transmitted with interrupt
generation if ITE=1. It is cleared by software
reading SR1 register followed by a read or write of
DR register. It is also cleared by hardware when
the interface is disabled (PE=0).
92/144
2
EVF
C STATUS REGISTER 1 (SR1)
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– SB=1 (Start condition generated)
– AF=1 (No acknowledge received after byte
– Address byte successfully transmitted.
0: Data byte received (if BTF=1)
1: Data byte transmitted
7
transmission if ACK=1)
54. It is also cleared by hardware when the
0
TRA
0
BTF
0
M/IDL
SB
0
– Following a byte transmission, this bit is set after
– Following a byte reception, this bit is set after
The SCL line is held low while BTF=1.
Bit 2 = Reserved. Forced to 0 by hardware.
Bit 1 = M/IDL Master/Idle.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after generating a Stop condition on
the bus. It is also cleared when the interface is
disabled (PE=0).
Bit 0 = SB Start bit generated.
This bit is set by hardware as soon as the Start
condition
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disabled
(PE=0).
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV2 event (See
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
0: Byte transfer not done
1: Byte transfer succeeded
0: Idle mode
1: Master mode
0: No Start condition
1: Start condition generated
is
generated
Figure
(following
54). BTF is
a
write