ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 118

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
PWM/BRM GENERATOR (Cont’d)
BRM Generation
The BRM bits allow the addition of a pulse to widen
a standard PWM pulse for specific PWM cycles.
This has the effect of “fine-tuning” the PWM Duty
cycle (without modifying the base duty cycle), thus,
with the external filtering, providing additional fine
voltage steps.
The incremental pulses (with duration of T
added to the beginning of the original PWM pulse.
The PWM intervals which are added to are
specified in the 4-bit BRM register and are
encoded as shown in the following table. The BRM
values shown may be combined together to
provide a summation of the incremental pulse
intervals specified.
The pulse increment corresponds to the PWM
resolution.
For example,if
– Data 18h is written to the PWM register
– Data 06h (00000110b) is written to the BRM reg-
– with a 8MHz internal clock (125ns resolution)
Figure 72. BRM pulse addition (PWM > 0)
118/144
ister
T
m = 0
CPU
x 64
T
m = 1
CPU
x 64
CPU
T
) are
CPU
T
m = 2
CPU
x 64 increment
x 64
Then 3.0
intervals,
2,4,6,10,12,14, where the pulse is broadened to
3.125 s.
Note: If 00h is written to both PWM and BRM registers,
An output can be set to a continuous “1” level by
clearing the PWM and BRM values and setting
POL = “1” (inverted polarity) in the PWM register.
This allows a PWM/BRM channel to be used as an
additional I/O pin if the DAC function is not
required.
Table 28. Bit BRM Added Pulse Intervals
(Interval #0 not selected).
BRM 4 - Bit Data
the generator output will remain at “0”. Conversely,
if both registers hold data 3Fh and 0Fh, respective-
ly, the output will remain at “1” for all intervals #1 to
#15, but it will return to zero at interval #0 for an
amount of time corresponding to the PWM resolu-
tion (T
0000
0001
0010
0100
1000
CPU
s-long pulse will be output at 8
except
).
none
i = 8
i = 4,12
i = 2,6,10,14
i = 1,3,5,7,9,11,13,15
Incremental Pulse Intervals
for
T
m = 15
CPU
x 64
cycles
numbered
s