ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 53

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
Bit 7 = ICF1 Input Capture Flag 1.
Bit 6 = OCF1 Output Compare Flag 1.
Bit 5 = TOF Timer Overflow.
Note: Reading or writing the ACLR register does not clear
Bit 4 = ICF2 Input Capture Flag 2.
Bit 3 = OCF2 Output Compare Flag 2.
ICF1
0: No input capture (reset value).
1: An input capture has occurred. To clear this
0: No match (reset value).
1: The content of the free running counter has
0: No timer overflow (reset value).
1:The free running counter rolled over from
0: No input capture (reset value).
1: An input capture has occurred.To clear this
0: No match (reset value).
1: The content of the free running counter has
7
bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) regis-
ter.
matched the content of the OC1R register. To
clear this bit, first read the SR register, then
read or write the low byte of the OC1R
(OC1LR) register.
FFFFh to 0000h. To clear this bit, first read
the SR register, then read or write the low
byte of the CR (CLR) register.
bit, first read the SR register, then read or
write the low byte of the IC2R (IC2LR) regis-
ter.
matched the content of the OC2R register. To
clear this bit, first read the SR register, then
read or write the low byte of the OC2R
(OC2LR) register.
TOF.
OCF1
TOF
ICF2
OCF2
0
Bit 2-0 = Unused.
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the
input capture 1 event).
OUTPUT
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
OUTPUT
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
MSB
MSB
MSB
7
7
7
COMPARE
COMPARE
ST72774/ST727754/ST72734
1
1
HIGH
LOW
REGISTER
REGISTER
53/144
LSB
LSB
LSB
0
0
0