ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 87

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

4.7 I²C SINGLE MASTER BUS INTERFACE (I2C)
4.7.1 Introduction
The I
between the microcontroller and the serial I
It provides single master functions, and controls all
I
It supports fast I²C mode (400kHz).
4.7.2 Main Features
4.7.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I
and a Fast I
software.
Figure 52. I
2
C bus-specific sequencing, protocol and timing.
– Parallel bus /I
– Interrupt generation
– Standard I
– 7-bit Addressing
I
– End of byte transmission flag
– Transmitter/Receiver flag
– Clock generation
2
C single Master Mode
2
C Bus Interface serves as an interface
2
SCL
SDA
C BUS Protocol
2
C bus. This selection is made by
2
C mode /Fast I
CONDITION
2
C protocol converter
START
2
MSB
C mode
1
2
2
2
C bus.
C bus
2
C
Mode Selection
The interface can operate in the two following
modes:
– Master transmitter/receiver
By default, it is idle.
The interface automatically switches from idle to
master after it generates a START condition and
from master to idle after it generates a STOP
condition.
Communication Flow
The interface initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start
condition is the address byte.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to
Figure
52.
8
ST72774/ST727754/ST72734
ACK
9
CONDITION
STOP
VR02119B
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