ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 111

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

DDC INTERFACE (Cont’d)
DDC STATUS REGISTER 1 (SR1)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event
occurs. It is cleared by software reading SR2
register in case of error event or as described in
Figure
interface is disabled (PE=0).
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after
detection of Stop condition (STOPF=1) or when
the interface is disabled (PE=0).
EVF
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
– AF=1 (No acknowledge received after byte
– STOPF=1 (Stop condition detected in Slave
– BERR=1 (Bus error, misplaced Start or Stop
0: Data byte received (if BTF=1)
1: Data byte transmitted
7
while ACK=1)
transmission if ACK=1)
mode)
condition detected)
67. It is also cleared by hardware when the
0
TRA
BUSY
BTF
ADSL
0
0
0
Bit 4 = BUSY Bus busy .
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. This information is still
updated when the interface is disabled (PE=0).
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is
correctly received or transmitted with interrupt
generation if ITE=1. It is cleared by software
reading SR1 register followed by a read or write of
DR register. It is also cleared by hardware when
the interface is disabled (PE=0).
– Following a byte transmission, this bit is set after
– Following a byte reception, this bit is set after
The SCL line is held low while BTF=1.
Bit 2 = ADSL Address matched (Slave mode). This
bit is set by hardware as soon as the received
slave address matched with the OAR register
content or the Enhanced DDC address is
recognized. An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register or by
hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
Bit 1:0 = Reserved. Forced to 0 by hardware.
reception of the acknowledge clock pulse. . BTF
is cleared by reading SR1 register followed by
writing the next byte in DR register.
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
0: No communication on the bus
1: Communication ongoing on the bus
0: Byte transfer not done
1: Byte transfer succeeded
0: Address mismatched or not received
1: Received address matched
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